verilog_hw1

full adder, ripple carry adder

Full adder
    Design a four-bits full adder using Gate Level Verilog.
    (tip : 先寫1bit的半加器再用module做出全部4bit的全加器)

Ripple carry adder
    Design a four-bits full-adder using dataflow level Verilog.
    Design a 16-bits ripple-carry-adder by combining four four-bits full adders.
    (tip : 用module)